SEMICONDUCTOR MEMORY DEVICE FOR SUPPRESSING VARIATIONS OF IMPURITY CONCENTRATIONS
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United States of America
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Issued Date -
Apr 14, 2022
app pub date -
Dec 22, 2021
filing date -
Dec 22, 2021
priority date (Note) -
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Abstract
A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
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