METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR PACKAGING SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION (STI)
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United States of America
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Issued Date -
Feb 3, 2022
app pub date -
Oct 18, 2021
filing date -
Oct 18, 2021
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Abstract
A method for manufacturing a semiconductor device includes forming a source region, a drain region, and a gate dielectric layer and a gate electrode covering a channel region between the source region and the drain region, forming an insulating layer over the source region, the drain region, and the gate electrode, forming first to third vias penetrating the insulating layer and exposing portions of the source region, the drain region, and the gate electrode, respectively, forming a source contact in the first via to electrically connect to the source region, forming a drain contact in the second via to electrically connect to the drain region, and forming a gate contact in the third via to electrically connect to the gate electrode. One or more of the first to third vias is formed by ion bombarding by a focused ion beam and followed by a thermal annealing process.
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