Method Of Forming Split Gate Memory Cells With Thinner Tunnel Oxide

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20220013531A1
SERIAL NO

17179057

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Abstract

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A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.

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Patent Owner(s)

Patent OwnerAddress
SILICON STORAGE TECHNOLOGY INC450 HOLGER WAY SAN JOSE CA 95134

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
DO, Nhan Saratoga, US 220 1249
FAN, Boolean Hsinchu, TW 1 1
WU, Man-Tang Hsinchu, TW 18 229
YANG, Jeng-Wei Zhubei City, TW 32 312

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