NONVOLATILE MEMORY APPARATUS FOR MITIGATING READ DISTURBANCE AND SYSTEM USING THE SAME
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Dec 30, 2021
app pub date -
Sep 10, 2021
filing date -
Sep 10, 2021
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully