Digital linear regulator clamping method and apparatus

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11429172
APP PUB NO 20210208656A1
SERIAL NO

16735563

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Abstract

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A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD M/S SC4-202 SANTA CLARA CA 95052-5326

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ahmed, Khondker Hillsboro, US 12 28
Angel, Nimrod Haifa, IL 11 44
Gihon, Arik Rishon le Zion, IL 16 41
Gorbatov, Eugene Hillsboro, US 81 1058
Gunther, Stephen Beaverton, US 10 116
Krishnamurthy, Harish Beaverton, US 36 232
Lehwalder, Philip Hillsboro, US 5 9
Leung, Patrick Portland, US 23 1305
Lyakhov, Alexander Portland, US 29 145
Pandit, Vishram Bangalore, IN 1 1
Shekhar, Sameer Portland, US 28 68
Uan-Zo-Li, Alexander Hillsboro, US 16 122
Zelikson, Michael Haifa, IL 35 245

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