CLOCK MULTIPLIER

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United States of America Patent

PATENT NO 20210203313
APP PUB NO 20210203313A1
SERIAL NO

17010854

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Abstract

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A clock multiplier is provided. The clock multiplier includes a delay line, an output clock generator, and a delay controller. The delay line receives an input clock and delays the input clock according to a selection signal group with multiple bits to provide a plurality of delayed clocks and a feedback clock. The output clock generator performs a logic operation on the input clock and a portion of the delayed clocks to generate an output clock. A frequency of the output clock is an integer multiple of a frequency of the input clock. The delay controller adjusts the selection signal group according to a timing difference between the input clock and the feedback clock, so that a transition point of the feedback clock approaches a transition point of the input clock.

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Patent Owner(s)

  • NUVOTON TECHNOLOGY CORPORATION

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  • 2020 Application Filing Year
  • H03K Class
  • 2472 Applications Filed
  • 1851 Patents Issued To-Date
  • 74.88 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2020202120222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Pao-Shu Hsinchu, TW 9 23
Cheng, Yuan-Po Hsinchu, TW 8 7

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges14751179187101 - 1011 - 2021 - 3051 - 6001002003004005006007008009001000110012001300140015001600

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