CLOCK MULTIPLIER
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 8, 2021
Grant Date -
Jul 1, 2021
app pub date -
Sep 3, 2020
filing date -
Dec 25, 2019
priority date (Note) -
Published
status (Latency Note)
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Importance

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Abstract
A clock multiplier is provided. The clock multiplier includes a delay line, an output clock generator, and a delay controller. The delay line receives an input clock and delays the input clock according to a selection signal group with multiple bits to provide a plurality of delayed clocks and a feedback clock. The output clock generator performs a logic operation on the input clock and a portion of the delayed clocks to generate an output clock. A frequency of the output clock is an integer multiple of a frequency of the input clock. The delay controller adjusts the selection signal group according to a timing difference between the input clock and the feedback clock, so that a transition point of the feedback clock approaches a transition point of the input clock.
First Claim
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Family
Country | kind | publication No. | Filing Date | Type | Sub-Type |
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- NUVOTON TECHNOLOGY CORPORATION
International Classification(s)

- 2020 Application Filing Year
- H03K Class
- 2472 Applications Filed
- 1851 Patents Issued To-Date
- 74.88 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Chang, Pao-Shu | Hsinchu, TW | 9 | 23 |
# of filed Patents : 9 Total Citations : 23 | |||
Cheng, Yuan-Po | Hsinchu, TW | 8 | 7 |
# of filed Patents : 8 Total Citations : 7 |
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- H03K Class
- 0 % this patent is cited more than
- 4 Age
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