Efficient logic blocks architectures for dense mapping of multipliers
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United States of America Patent
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Sep 26, 2023
Grant Date -
Jul 1, 2021
app pub date -
Dec 27, 2019
filing date -
Dec 27, 2019
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit includes a logic block configured to perform multiplication operations. The logic block includes a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs. Additionally, the logic block includes adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs. Furthermore, the logic block includes circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
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Patent Citation Ranking
- 1 Citation Count
- G06F Class
- 79.11 % this patent is cited more than
- 2 Age
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