METHOD AND CIRCUITS FOR FINE-CONTROLLED PHASE/FREQUENCY OFFSETS IN PHASE-LOCKED LOOPS
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United States of America Patent
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Issued Date -
Jun 10, 2021
app pub date -
Oct 5, 2020
filing date -
Dec 19, 2017
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Abstract
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.
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