LOW DROPOUT LINEAR VOLTAGE REGULATOR
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United States of America Patent
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Issued Date -
Jan 21, 2021
app pub date -
Oct 16, 2017
filing date -
Jan 10, 2017
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Abstract
A low dropout linear voltage regulator is provided. In the low dropout linear voltage regulator, a power transistor has a source connected to a power source, a gate connected to an output terminal of an error amplifier, a drain connected to an output terminal of the low dropout linear voltage regulator. A dynamic Miller compensation network has a first terminal connected to the output terminal of the error amplifier, a second terminal connected to the output terminal of the low dropout linear voltage regulator. A controller has a first terminal connected to the gate of the power transistor, and a second terminal connected to a third terminal of the Miller compensation network. The controller is configured to detect a current at the output terminal of the low dropout linear voltage regulator and generate control signals according to the current to control connection and disconnection of each second resistance-capacitance branch in the dynamic Miller compensation network.
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