Relaxation oscillator with an aging effect reduction technique
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United States of America Patent
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Aug 17, 2021
Grant Date -
Dec 31, 2020
app pub date -
Nov 27, 2018
filing date -
Nov 28, 2017
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Abstract
A relaxation oscillator with an aging effect reduction technique comprises a comparator (CP) coupled with its input side (CP1, CP2) to a network comprising at least one capacitor (C, C1, C2), a plurality of transistors (M1, M2, M3, M4) and a plurality of controllable switches (SW11, . . . , SW8, SW111, . . . , SW180). The relaxation oscillator uses a switching method such that the roles of current/voltage generator's transistor and current mirror transistor are periodically swapping by the output signal of the relaxation oscillator. Reducing mismatch of operating points between current/voltage generator and current minor transistors achieves a decrease of frequency degradation caused by aging effect.
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