Semiconductor device
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United States of America Patent
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Oct 22, 2024
Grant Date -
Dec 31, 2020
app pub date -
Jun 18, 2020
filing date -
Jun 28, 2019
priority date (Note) -
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Abstract
To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.
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