DETERMINISTIC TEST PATTERN GENERATION FOR DESIGNS WITH TIMING EXCEPTIONS
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United States of America Patent
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Issued Date -
Dec 31, 2020
app pub date -
Aug 22, 2019
filing date -
Jun 26, 2019
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Abstract
Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.
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