Semiconductor device and method to minimize stress on stack via

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United States of America Patent

PATENT NO 12080600
APP PUB NO 20200402855A1
SERIAL NO

17010610

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Abstract

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A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

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Patent Owner(s)

Patent OwnerAddress
STATS CHIPPAC PTE LTD5 YISHUN STREET 23 SINGAPORE 768442

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chow, Seng Guan Singapore, SG 216 7432
Lin, Yaojian Jiangyin, CN 337 10584

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