Transistor Structure With A Stress Layer
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United States of America Patent
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Issued Date -
Nov 19, 2020
app pub date -
May 14, 2020
filing date -
May 15, 2019
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Abstract
A new transistor structure is disclosed. This new structure has a dielectric stress layer in a three-dimensional structure outside of the gate region for modulation or the characteristics of the transistor. Additionally, trenches are created in the region between the source electrode and the drain electrode in such a manner so as to create ridges that traverse the gate region.
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