READ CACHE MEMORY

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United States of America Patent

APP PUB NO 20200363962A1
SERIAL NO

16987055

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC8000 S FEDERAL WAY P O BOX 6 BOISE ID 83707

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Arcoleo, Mathew Campbell, US 4 30
Feng, Eugene San Jose, US 11 330

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