ELECTRICAL FUSE FORMATION DURING A MULTIPLE PATTERNING PROCESS
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United States of America Patent
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Oct 22, 2020
app pub date -
Jul 1, 2020
filing date -
Apr 23, 2018
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Abstract
Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
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