3-dimensional NOR string arrays in segmented stacks
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 23, 2021
Grant Date -
Oct 8, 2020
app pub date -
Apr 27, 2020
filing date -
Jun 20, 2017
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.
First Claim
Family
International Classification(s)
- C22B:PRODUCTION OR REFINING OF METALS
- H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....
- C25B:ELECTROLYTIC OR ELECTROPHORETIC PROCESSES FOR THE ....
- C07C:ACYCLIC OR CARBOCYCLIC COMPOUNDS
- B01J:CHEMICAL OR PHYSICAL PROCESSES, e.g. CATALYSIS, CO....
- C01G:COMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLAS....
- G11C:STATIC STORES
- C30B:SINGLE-CRYSTAL GROWTH
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully