Phase lock circuitry using frequency detection
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United States of America Patent
Stats
-
Nov 17, 2020
Grant Date -
Oct 1, 2020
app pub date -
Mar 28, 2019
filing date -
Mar 28, 2019
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.
First Claim
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Family
International Classification(s)
- 2019 Application Filing Year
- H03L Class
- 591 Applications Filed
- 495 Patents Issued To-Date
- 83.76 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- H03L Class
- 34.27 % this patent is cited more than
- 5 Age
Maintenance Fees
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|---|---|---|---|---|
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