TAMPER PROTECTION OF MEMORY DEVICES ON AN INTEGRATED CIRCUIT
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United States of America Patent
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Jun 4, 2020
app pub date -
Dec 4, 2018
filing date -
Dec 4, 2018
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Abstract
A data system includes an information bus, a volatile memory located on the information bus, and an MRAM located on the information bus. The data system includes threat detection circuitry. In response to a threat condition to the MRAM, data is transferred via the information bus from the MRAM to the volatile memory for storage during a threat to the MRAM as indicated by the threat condition. In some examples, the threat condition is characterized as a magnetic field exposure.
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