Load compensation to reduce deterministic jitter in clock applications
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United States of America Patent
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Sep 15, 2020
Grant Date -
May 21, 2020
app pub date -
Oct 23, 2019
filing date -
Nov 15, 2018
priority date (Note) -
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Abstract
A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.
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