Random telegraph signal noise reduction scheme for semiconductor memories
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United States of America Patent
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May 4, 2021
Grant Date -
Apr 2, 2020
app pub date -
Dec 2, 2019
filing date -
Jan 25, 2008
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Abstract
Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.
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