COHERENT OBSERVABILITY AND CONTROLLABILITY OF OVERLAID CLOCK AND DATA PROPAGATION IN EMULATION AND PROTOTYPING
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United States of America
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Mar 26, 2020
app pub date -
Sep 25, 2019
filing date -
Sep 25, 2019
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Abstract
The independent claims of this patent signify a concise description of embodiments. An emulation control block enables a user to view an entire design in the same phase so that the used can observe and control a halted design in the same logical reference cycle. Both the clock cone and design flops are provided in the state which occurs after the evaluation of cycle K of the reference time. During cycle K+1 of an emulation, the values of derived clocks for cycle K+1 are computed. Moreover, during cycle K+1 of the emulation, the values of the sequential elements are computed based cycle K values of the clocks. When the emulation is halted due to a break, the clock cone is reverted to its previous state. This Abstract is not intended to limit the scope of the claims.
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