HIGH VOLTAGE ARCHITECTURE FOR NON-VOLATILE MEMORY
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United States of America
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Feb 27, 2020
app pub date -
Aug 5, 2019
filing date -
Aug 5, 2019
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Abstract
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
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