PHASE LOCKED LOOP USING DIRECT DIGITAL FREQUENCY SYNTHESIZER

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20200026323A1
SERIAL NO

16474524

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Abstract

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The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system.

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Patent Owner(s)

Patent OwnerAddress
POSTECH ACADEMY-INDUSTRY FOUNDATION77 CHEONGAM-RO NAM-GU GYEONGSANGBUK-DO POHANG-SI 37673

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHO, Hwa Suk Daejeon, KR 3 11
SIM, Jae Yoon Pohang-si, KR 48 312

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