GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Jan 9, 2020
app pub date -
Jul 3, 2018
filing date -
Jul 3, 2018
priority date (Note) -
Published
status (Latency Note)
![]() |
A preliminary load of PAIR data current through [] has been loaded. Any more recent PAIR data will be loaded within twenty-four hours. |
PAIR data current through []
A preliminary load of cached data will be loaded soon.
Any more recent PAIR data will be loaded within twenty-four hours.
![]() |
Next PAIR Update Scheduled on [ ] |

Importance

US Family Size
|
Non-US Coverage
|
Abstract
A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a shield gate (404) having a single segment structure or a longitudinally arranged multiple segments structure; and an insulation silicon oxide (204) being filled between adjacent control gate and shield gate in vertical direction.

First Claim
Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
CSMC TECHNOLOGIES FAB2 CO LTD | 214028 NO 8 XINZHOU ROAD NATIONAL HI TECH INDUSTRIAL DEVELOPMENT ZONE WUXI JIANGSU WUXI CITY JIANGSU PROVINCE 214028 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Qi, Shukun | Jiangsu, CN | 10 | 13 |
Cited Art Landscape
- No Cited Art to Display

Patent Citation Ranking
Forward Cite Landscape
- No Forward Cites to Display

Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
---|---|---|---|---|
7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 9, 2027 |
11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 9, 2031 |
Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text

Legal Events

Matter Detail

Renewals Detail

Note
The template below is formatted to ensure compatibility with our system.
Provide tags with | separated like (tags1|tags2).
Maximum length is 128 characters for Customer Application No
Mandatory Fields * - 'MatterType','AppType','Country','Title','SerialNo'.
Acceptable Date Format - 'MM/DD/YYYY'.
Acceptable Filing/App Types -
- Continuation/Divisional
- Original
- Paris Convention
- PCT National
- With Priority
- EP Validation
- Provisional Conversion
- Reissue
- Provisional
- Foreign Extension
Acceptable Status -
- Pending
- Abandoned
- Unfiled
- Expired
- Granted
Acceptable Matter Types -
- Patent
- Utility Model
- Supplemental Protection Certificate
- Design
- Inventor Certificate
- Plant
- Statutory Invention Reg
Advertisement
Advertisement
Advertisement

Recipient Email Address

Recipient Email Address

Comment
Recipient Email Address

Success
E-mail has been sent successfully.
Failure
Some error occured while sending email. Please check e-mail and try again!
PAIR load has been initiated
A preliminary load of cached data will be loaded soon. Current PAIR data will be loaded within twenty four hours.
File History PDF
Thank you for your purchase! The File Wrapper for Patent Number 20200013864 will be available within the next 24 hours.
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:

Last Refreshed On:
Changes done successfully
Important Notes on Latency of Status data
Please note there is up to 60 days of latency in this Status indicator for certain status conditions. You can obtain up-to-date Status indicator readings by ordering PAIR for the file.
An application with the status "Published" (which means it is pending) may be recently abandoned, but not yet updated to reflect its abandoned status. However, an application filed less than one year ago is unlikely to be abandoned.
A patent with the status "Granted" may be recently expired, but not yet updated to reflect its expired status. However, it is highly unlikely a patent less than 3.5 years old would be expired.
An application with the status "Abandoned" is almost always current, but there is a small chance it was recently revived and the status not yet updated.
Important Note on Priority Date data
This priority date is an estimated earliest priority date and is purely an estimation. This date should not be taken as legal conclusion. No representations are made as to the accuracy of the date listed. Please consult a legal professional before relying on this date.
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.