APPARATUSES AND METHODS FOR PIN CAPACITANCE REDUCTION INCLUDING BOND PADS AND CIRCUITS IN A SEMICONDUCTOR DEVICE
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United States of America
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May 25, 2018
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May 25, 2018
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Apparatuses and methods for including bond pads and circuits in a semiconductor device are disclosed. An example apparatus includes a bond pad including one or more metal layers and one or more circuits. The circuits include one or more layers overlapped with the bond pad and coupled to metal layers of the bond pad. The pin capacitance can be reduced by overlapping of related layers and minimizing the areas of the unrelated layers.
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