Double data rate interpolating analog to digital converter
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United States of America Patent
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Sep 8, 2020
Grant Date -
Nov 21, 2019
app pub date -
Jul 31, 2019
filing date -
Jan 31, 2017
priority date (Note) -
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Abstract
A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.
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