Lower power auto-zeroing receiver incorporating CTLE, VGA, and DFE
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United States of America Patent
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Jun 2, 2020
Grant Date -
Sep 26, 2019
app pub date -
Mar 19, 2019
filing date -
Mar 20, 2018
priority date (Note) -
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Abstract
An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.
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