Cycle slip detection and correction in phase-locked loop
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United States of America Patent
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Jun 16, 2020
Grant Date -
Sep 12, 2019
app pub date -
Dec 13, 2018
filing date -
Mar 9, 2018
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Abstract
A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.
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