Normalizing error signal in analog-to-digital converter runaway state
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United States of America Patent
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May 26, 2020
Grant Date -
Jul 11, 2019
app pub date -
Mar 14, 2019
filing date -
Feb 2, 2017
priority date (Note) -
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status (Latency Note)
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Abstract
In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.
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