Process integration approach of selective tungsten via fill

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United States of America Patent

PATENT NO 10727119
APP PUB NO 20190157145A1
SERIAL NO

16252100

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Abstract

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Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.

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Patent Owner(s)

Patent OwnerAddress
APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ai, Hua Tracy, US 17 1563
Banthia, Vikash Los Altos, US 33 1188
Lei, Yu Belmont, US 136 1885
Ma, Feiyue San Jose, US 10 66
Naik, Mehul B San Jose, US 58 1313
Ren, He San Jose, US 81 1752
Wu, Kai Palo Alto, US 492 3966
Wu, Zhiyuan San Jose, US 63 1267

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