METHODS FOR FORMING IC STRUCTURE HAVING RECESSED GATE SPACERS AND RELATED IC STRUCTURES
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United States of America Patent
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Issued Date -
May 2, 2019
app pub date -
Nov 2, 2017
filing date -
Nov 2, 2017
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Abstract
The present disclosure relates to methods for forming IC structures having recessed gate spacers and related IC structures. A method may include: forming a first and second dummy gate over a fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer and a second gate spacer, the opening exposing a source/drain region; recessing the first and second gate spacers; forming an etch stop layer within the opening such that the etch stop layer extends vertically along the recessed first and second gate spacers; forming a dielectric fill over the etch stop layer to substantially fill the opening; replacing the first and second dummy gates with first and second RMG structures; recessing the first and second RMG structures; and forming a gate cap layer over the first and second RMG structures.
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