Embedded sonos with triple gate oxide and manufacturing method of the same
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United States of America Patent
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Sep 22, 2020
Grant Date -
Mar 21, 2019
app pub date -
Aug 8, 2018
filing date -
Jun 14, 2017
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Abstract
A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.
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