METHOD OF APPLYING VERTEX BASED CORRECTIONS TO A SEMICONDUCTOR DESIGN
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Sep 20, 2018
app pub date -
Dec 22, 2015
filing date -
Dec 22, 2015
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A method of geometry corrections to properly transfer semiconductor designs on a wafer or a mask in nanometer scale processes is provided. In contrast with some prior art techniques, geometry corrections and possibly dose corrections are applied before fracturing. Unlike edge based corrections, where the edges are displaced in parallel, the displacements applied to generated geometry corrections do not preserve parallelism of the edges, which is specifically well suited for free form designs. A seed design is generated from the target design. Vertices connecting segments are placed along the seed design contour. Correction sites are placed on the segments. Displacement vectors are applied to the vertices. A simulated contour is generated and compared to the contour of the target design. The process is iterated until a match criteria between simulated and target design (or another stop criteria) is reached.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully