Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET

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United States of America Patent

PATENT NO 10914703
APP PUB NO 20180156749A1
SERIAL NO

15827206

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Abstract

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Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps:

    measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets NW,width WW,i, of the nanowire/nanosheet number i, i being an integer from 1 to NW,thickness of the nanowire/nanosheet HW,i, number i, i being an integer from 1 to NW,corner radius RW,i of the nanowire/nanosheet number i, i being an integer from 1 to NW, RW,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ϕT given by ϕT=kBT/q;measuring the total gate capacitance for a plurality of gate voltages;determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowires/nanosheets MOSFET.

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COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES25 RUE LEBLANC BATIMENT "LE PONANT D" PARIS 75015

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  • 2017 Application Filing Year
  • H01L Class
  • 30754 Applications Filed
  • 25260 Patents Issued To-Date
  • 82.14 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2017201820192020202120222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jaud, Marie-Anne Claix, FR 6 695
Lacord, Joris La Murette, FR 5 17
Martinie, Sébastien Saint-Martin le Vinoux, FR 1 14
Poiroux, Thierry Voiron, FR 22 163
Rozeau, Olivier Moirans, FR 12 83

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  • 2 Citation Count
  • H01L Class
  • 52.76 % this patent is cited more than
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