Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET
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United States of America Patent
Stats
-
Feb 9, 2021
Grant Date -
Jun 7, 2018
app pub date -
Nov 30, 2017
filing date -
Dec 2, 2016
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps:
- measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets NW,width WW,i, of the nanowire/nanosheet number i, i being an integer from 1 to NW,thickness of the nanowire/nanosheet HW,i, number i, i being an integer from 1 to NW,corner radius RW,i of the nanowire/nanosheet number i, i being an integer from 1 to NW, RW,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ϕT given by ϕT=kBT/q;measuring the total gate capacitance for a plurality of gate voltages;determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowires/nanosheets MOSFET.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES | 25 RUE LEBLANC BATIMENT "LE PONANT D" PARIS 75015 |
International Classification(s)

- 2017 Application Filing Year
- H01L Class
- 30754 Applications Filed
- 25260 Patents Issued To-Date
- 82.14 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Jaud, Marie-Anne | Claix, FR | 6 | 695 |
# of filed Patents : 6 Total Citations : 695 | |||
Lacord, Joris | La Murette, FR | 5 | 17 |
# of filed Patents : 5 Total Citations : 17 | |||
Martinie, Sébastien | Saint-Martin le Vinoux, FR | 1 | 14 |
# of filed Patents : 1 Total Citations : 14 | |||
Poiroux, Thierry | Voiron, FR | 22 | 163 |
# of filed Patents : 22 Total Citations : 163 | |||
Rozeau, Olivier | Moirans, FR | 12 | 83 |
# of filed Patents : 12 Total Citations : 83 |
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Patent Citation Ranking
- 2 Citation Count
- H01L Class
- 52.76 % this patent is cited more than
- 4 Age
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Full Text
- measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets Nw,width Ww,i, of the nanowire/nanosheet number i, i being an integer from 1 to Nw,thickness of the nanowire/nanosheet Hw,i, number i, i being an integer from 1 to Nw,corner radius Rw,i of the nanowire/nanosheet number i, i being an integer from 1 to Nw, Rw,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ΦT given by ΦT=kBT/q;measuring the total gate capacitance for a plurality of gate voltages;determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowires/nanosheets MOSFET.

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