PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications
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United States of America Patent
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Jan 1, 2019
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May 17, 2018
app pub date -
Nov 17, 2016
filing date -
Nov 17, 2016
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Abstract
An ADPLL circuit includes a time-to-digital converter (TDC) configured to generate a signal indicative of a phase difference between a first signal and a reference signal and a doubler electrically coupled to the TDC. The doubler is configured to receive a first voltage signal and generate a second voltage signal. The second voltage signal is provided to a voltage input of the TDC. The TDC is configured to generate one or more control signals for the doubler to adjust the second voltage signal.
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