Systems and methods for producing flat surfaces in interconnect structures
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United States of America Patent
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Oct 13, 2020
Grant Date -
Apr 12, 2018
app pub date -
Dec 7, 2017
filing date -
Jun 24, 2011
priority date (Note) -
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Abstract
In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, “first” layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.
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