Method and machine for examining wafers

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United States of America Patent

PATENT NO 10840156
APP PUB NO 20180076099A1
SERIAL NO

15708060

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Abstract

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Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and/or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time.

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Patent Owner(s)

Patent OwnerAddress
ASML NETHERLANDS B VP O BOX 324 VELDHOVEN 5500 AH

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chou, Chien-Hung San Jose, US 42 826
Tai, Wen-Tin Fremont, US 3 10

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