SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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app pub date -
Dec 9, 2016
filing date -
Aug 30, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor package includes a first chip, a second chip, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip includes a first active surface having a chip bonding zone, a plurality of first inner pads in the chip bonding zone and a plurality of first outer pads out of the chip bonding zone. The second chip is flipped on the chip bonding zone. The first conductive bumps are disposed on the first outer pads. The second conductive bumps are disposed between the first inner pads of the first chip and a plurality of second pads of the second chip. The underfill is disposed on the first active surface and covers the second conductive bumps, at least a part of each second chip lateral and at least a part of each first conductive bump. Multiple semiconductor package manufacturing methods are further provided.
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Patent Citation Ranking
- 3 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age