Connection verification technique
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United States of America Patent
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Jul 21, 2020
Grant Date -
Feb 15, 2018
app pub date -
Oct 27, 2017
filing date -
Dec 30, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed, as are additional techniques for detecting excess temperature and enabling special functionalities using multi-stage connection pads.
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