Ramp based clock synchronization for stackable circuits
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United States of America Patent
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Jul 30, 2019
Grant Date -
Feb 1, 2018
app pub date -
Jul 28, 2016
filing date -
Jul 28, 2016
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Abstract
A phase generation circuit is disclosed. The circuit includes a ramp generation circuit arranged to generate a ramp signal in synchronization with a synchronization clock signal. A phase selection circuit generates a reference signal in response to a phase selection signal. A comparator has a first input terminal coupled to receive the ramp signal and a second input terminal coupled to receive the reference signal. The comparator produces a phase clock signal at an output terminal.
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