System and method for providing an area efficient and design rule check (DRC) friendly power sequencer for digital circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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N/A
Issued Date -
Feb 1, 2018
app pub date -
Sep 29, 2016
filing date -
Aug 1, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
According to one general aspect, an apparatus may include a power header and a logic circuit. The power header may include a gate terminal, a first channel terminal, a second channel terminal, and a bulk terminal coupled with a first voltage power signal. The power header may be configured to perform one of dynamically coupling or decoupling a logic circuit with the first voltage power signal. The logic circuit may include a bulk terminal coupled with a second voltage power signal and a power terminal that is either dynamically coupled or decoupled, as determined by the power header, with the first voltage power signal. A power sequencing signal may be included in the apparatus and may be configured to control the power header such that, when active, the power header couples the logic circuit with the first voltage power signal after the second voltage power signal is high.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2016 Application Filing Year
- H03K Class
- 2511 Applications Filed
- 2079 Patents Issued To-Date
- 82.80 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- H03K Class
- 21.67 % this patent is cited more than
- 7 Age
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