Three dimensional monolithic LDMOS transistor
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United States of America Patent
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Mar 19, 2019
Grant Date -
Feb 1, 2018
app pub date -
Oct 12, 2017
filing date -
May 26, 2015
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Abstract
A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source I drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.
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