NON-VOLATILE MEMORY WITH REDUCED VARIATIONS IN GATE RESISTANCE
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United States of America Patent
Stats
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N/A
Issued Date -
Feb 1, 2018
app pub date -
Feb 28, 2017
filing date -
Jul 27, 2016
priority date (Note) -
Published
status (Latency Note)
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Importance

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Abstract
A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
SANDISK TECHNOLOGIES LLC | 6900 DALLAS PARKWAY SUITE 325 PLANO TX 75024 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Baraskar, Ashish | Santa Clara, US | 36 | 323 |
# of filed Patents : 36 Total Citations : 323 | |||
Chen, Jian | San Jose, US | 1588 | 23569 |
# of filed Patents : 1588 Total Citations : 23569 | |||
Lee, Yao-Sheng | Tampa, US | 80 | 5063 |
# of filed Patents : 80 Total Citations : 5063 | |||
Lu, Ching-Huang | Fremont, US | 119 | 1023 |
# of filed Patents : 119 Total Citations : 1023 | |||
Makala, Raghuveer S | Campbell, US | 261 | 7645 |
# of filed Patents : 261 Total Citations : 7645 |
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Patent Citation Ranking
- 6 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
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