NON-VOLATILE MEMORY WITH REDUCED VARIATIONS IN GATE RESISTANCE

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United States of America Patent

APP PUB NO 20180033798A1
SERIAL NO

15445409

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Abstract

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A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

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Patent Owner(s)

Patent OwnerAddress
SANDISK TECHNOLOGIES LLC6900 DALLAS PARKWAY SUITE 325 PLANO TX 75024

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Baraskar, Ashish Santa Clara, US 36 323
Chen, Jian San Jose, US 1588 23569
Lee, Yao-Sheng Tampa, US 80 5063
Lu, Ching-Huang Fremont, US 119 1023
Makala, Raghuveer S Campbell, US 261 7645

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  • 6 Citation Count
  • H01L Class
  • 23.71 % this patent is cited more than
  • 7 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges3689997611243481558461392216162801 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05001000150020002500300035004000450050005500600065007000750080008500900095001000010500

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