Methods of fabricating integrated circuits and devices with interleaved transistor elements
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 7, 2019
Grant Date -
Feb 1, 2018
app pub date -
Sep 29, 2017
filing date -
Oct 19, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.
First Claim
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International Classification(s)
- 2017 Application Filing Year
- H03K Class
- 2832 Applications Filed
- 2220 Patents Issued To-Date
- 78.39 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H03K Class
- 0 % this patent is cited more than
- 6 Age
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