Semiconductor die singulation and structures formed thereby
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United States of America Patent
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Jul 21, 2020
Grant Date -
Feb 1, 2018
app pub date -
Dec 9, 2016
filing date -
Jul 29, 2016
priority date (Note) -
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Abstract
An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.
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