Etch damage and ESL free dual damascene metal interconnect
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United States of America Patent
Stats
-
Jun 4, 2019
Grant Date -
Feb 1, 2018
app pub date -
Oct 6, 2017
filing date -
Jun 19, 2012
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.
First Claim
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International Classification(s)
- 2017 Application Filing Year
- H01L Class
- 30754 Applications Filed
- 25260 Patents Issued To-Date
- 82.14 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- H01L Class
- 32.24 % this patent is cited more than
- 6 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Dec 4, 2026 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Dec 4, 2030 |
