Semiconductor memory device and method of operating the same
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United States of America Patent
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May 15, 2018
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N/A
app pub date -
Oct 5, 2017
filing date -
Jun 21, 2013
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Abstract
A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line.
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