Multiple register memory access instructions, processors, methods, and systems
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 16, 2018
Grant Date -
Feb 1, 2018
app pub date -
Oct 9, 2017
filing date -
Jun 28, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2017 Application Filing Year
- G06F Class
- 61356 Applications Filed
- 46481 Patents Issued To-Date
- 75.76 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- G06F Class
- 20.77 % this patent is cited more than
- 7 Age
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|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Apr 16, 2026 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Apr 16, 2030 |
