Systems and methods for generating a multiple patterning lithography compliant integrated circuit layout
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 12, 2018
Issued Date -
N/A
app pub date -
Jul 28, 2016
filing date -
Jul 28, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Computer-implemented systems and methods for generating a multiple patterning lithography (MPL) compliant integrated circuit layout are provided. A plurality of integrated circuit (IC) cells are assembled to form an IC layout. The IC layout includes at least two IC cells that abut one another. After the assembling of the IC cells, a decomposition algorithm is executed to assign multiple colors to design shapes within the IC layout. Multiple patterning coloring conflicts are detected in the IC layout after the assigning of the colors to the design shapes. A fixing algorithm is executed, under which a conflict present in two abutting IC cells is fixed by flipping or shifting at least one of the abutting IC cells.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully